1. Field of the Invention
This invention relates to an integrated circuit and method of operation of such a circuit, and in particular to integrated circuits that use serial test scan chains for applying signals to and capturing signals from predetermined circuit elements within an integrated circuit.
2. Description of the Prior Art
Integrated circuit testing using serial test scan chains is known from the JTAG system that is the subject of IEEE Standard 1149.1-1990. In accordance with this Standard, an entire integrated circuit is treated as a whole and tested together.
However, as the complexity of integrated circuits has increased, it has become more desirable to test individual circuit elements within the integrated circuit, and accordingly integrated circuits have been developed which incorporate a number of separate serial test scan chains, each being coupled to a different circuit element to be tested.
Typically, testing hardware external to the integrated circuit will access the test scan chain via a scan chain controller provided on the integrated circuit, the scan chain controller having a serial interface for communicating with the testing hardware.
Where multiple serial test scan chains are provided, it is known to provide a scan chain selecting instruction which is decoded by the scan chain controller to cause the scan chain controller to capture a scan chain specifying value received at the serial interface, and to use that scan chain specifying value to select a serial test scan chain upon which further instructions received at said serial interface are to be effected. A description of such a scan chain selecting instruction is provided in U.S. Pat. No. 5,636,227.
Hence, to specify an instruction to be applied in relation to a desired scan chain, it is first necessary to scan a scan chain selecting instruction into the scan chain controller, then to scan the appropriate scan chain specifying value into the scan chain controller, and then to scan in the actual instruction to be applied. It has been found that this process can impact on the efficiency of the testing procedure, particularly in scenarios where this process is repeated many times.
Accordingly, it would be desirable to improve the efficiency of the testing procedure when the above process is required.
Viewed from a first aspect, the present invention provides an integrated circuit comprising: a plurality of circuit elements; a plurality of serial test scan chains each coupled to a different one of said circuit elements; a scan chain selector responsive to a specified scan chain specifying value to select a corresponding one of said plurality of test scan chains; a scan chain controller having a serial interface for receiving signals from outside of said integrated circuit, said scan chain controller comprising an instruction decoder for decoding scan chain controller instructions received from said serial interface; the decoder being responsive to a first scan chain controller instruction to specify a predetermined scan chain specifying value and a second scan chain controller instruction for decoding by the decoder.
It has been found that there are a number of testing procedures where much of the testing involves using only a subset of the scan chain controller instructions in relation to a subset of the available test scan chains. Given this fact, the present invention specifies a first scan chain controller instruction that is arranged to cause the decoder to specify a predetermined scan chain specifying value and a second scan chain controller instruction. Accordingly, in situations where the predetermined scan chain specifying value corresponds to a frequently used scan chain, and the second scan chain controller instruction is a frequently used instruction in relation to that scan chain, then the use of the first scan chain controller instruction can significantly improve the efficiency of the testing procedure by avoiding the requirement for the multi-step process described earlier each time that instruction is to be applied in relation to that scan chain.
In preferred embodiments, the integrated circuit further comprises: an instruction register for storing a scan chain controller instruction to be decoded by the decoder; and a scan chain register for storing a scan chain specifying value to be referenced by the scan chain selector to determine which test scan chain to select. Typically, both the instruction register and the scan chain register will reside within the scan chain controller, as will the scan chain selector in preferred embodiments.
In one embodiment, the decoder may be arranged to be responsive to the first scan chain controller instruction to cause the predetermined scan chain specifying value to be written into the scan chain register, and the second scan chain controller instruction to be written into the instruction register.
However, it has been found that a more efficient approach is to cause the decoder to simulate appropriate outputs from the instruction register and the scan chain register without actually storing either the predetermined scan chain specifying value or the second scan chain controller instruction in the scan chain register and instruction register, respectively. More particularly, in preferred embodiments, the decoder is responsive to the first scan chain controller instruction to simulate as the output of the instruction register the second scan chain controller instruction and to simulate as the output of the scan chain register the predetermined scan chain specifying value without the contents of the instruction register and scan chain register being updated.
In preferred embodiments, the integrated circuit further comprises a first multiplexer located between the instruction register and the decoder having a first input connected to the instruction register and a second input arranged to receive the second scan chain controller instruction, the decoder incorporating a pre-decoder responsive to the first scan chain controller instruction to cause the first multiplexer to output the instruction received at the second input. It will be appreciated that the first multiplexer and pre-decoder can be incorporated as part of the decoder itself. However, by embodying the first multiplexer and the pre-decoder function as a separate logical function to the remainder of the decoder, this avoids the requirement to make any alterations to the instruction decoder itself.
Further, in preferred embodiments, the integrated circuit further comprises a second multiplexer located between the scan chain register and the scan chain selector having a first input connected to the scan chain register and a second input arranged to receive the predetermined scan chain specifying value, the pre-decoder being responsive to the first scan chain controller instruction to cause the second multiplexer to output the data received at the second input.
It will be appreciated that the above described techniques could be employed in relation to the testing of a variety of different circuit elements that have scan chains associated therewith. However, in preferred embodiments, one of the circuit elements is an instruction transfer register for specifying an instruction to be executed by a microprocessor of the integrated circuit, and the predetermined scan chain specifying value identifies a test scan chain incorporating a shift register for shifting data into said instruction transfer register. In these preferred embodiments, the testing procedure is actually used not to test the integrated circuit as such, but to debug applications executing on the integrated circuit. In particular the testing mechanism of the invention is used to access on-chip hardware such as the instruction transfer register to enable application debugging.
In such preferred embodiments, the decoder is preferably responsive to the second scan chain controller instruction to cause the scan chain selector to be coupled to the serial interface to enable instruction data received at the serial interface to be passed to the shift register of the test scan chain identified by the predetermined scan chain specifying value. Hence, decoding of the first scan chain controller instruction will cause the test scan chain associated with the instruction transfer register to be selected, and the scan chain selector to be coupled to the serial interface to enable instruction data to subsequently be passed in through the serial interface to the shift register of the test scan chain.
Further, in preferred embodiments, once the instruction data has been shifted into the shift register, it is written into the instruction transfer register, and the microprocessor is caused to execute the instruction specified by the instruction data, with the resulting data being written to a data transfer register. In preferred embodiments, the second scan chain controller instruction that is specified via the first scan chain controller instruction actually causes the coupling of the scan chain selector to the serial interface, and the subsequent writing of the instruction data into the instruction transfer register from the shift register. Preferably, the scan chain controller then returns to a mode of operation which, in combination with the second scan chain controller instruction still being set, causes a signal to be issued to the microprocessor to cause it to execute the instruction specified by the instruction data in the instruction transfer register.
In many situations, it is also desirable to look at the data written into the data transfer register as a result of the microprocessor executing the instruction within the instruction transfer register. Accordingly, in preferred embodiments, the data transfer register is also one of the circuit elements, and the scan chain register is arranged to store the scan chain specifying value identifying the test scan chain coupled to the data transfer register, that test scan chain incorporating a shift register for shifting data into and out of said data transfer register. In preferred embodiments, the scan chain specifying value for the test scan chain coupled to the data transfer register can be stored in the scan chain register even before the first scan chain controller instruction is executed, since in preferred embodiments, execution of the first scan chain controller instruction does not require the contents of the scan chain register to be updated, since instead a simulated output of the scan chain register is produced.
In preferred embodiments, once data has been written to the data transfer register, a third scan chain controller instruction is input to the scan chain controller, the decoder being responsive to the third scan chain controller instruction to cause the scan chain selector to be coupled to the serial interface to enable the data in the data transfer register to be stored into the shift register of the test scan chain coupled to the data transfer register and then output over the serial interface.
It has been found that in such preferred embodiments, where instruction data is to be written to the instruction transfer register, the microprocessor is then to execute the instruction and store the resultant data in the data transfer register, and that data is then to be read out by the serial interface, the use of the first scan chain controller instruction is particularly beneficial. This is because the scan chain specifying value for the test scan chain coupled to the data transfer register can be stored into the scan chain register, and the first scan chain controller instruction can then be decoded to cause the test scan chain associated with the instruction transfer register to be used to load an instruction into the instruction transfer register (even though that test scan chain is not the one indicated by the contents of the scan chain register). This can then be followed merely by the third scan chain controller instruction to cause the resulting data to be read out from the data transfer register into the associated test scan chain, and then output from the integrated circuit via the serial interface, since the scan chain register already identifies the test scan chain coupled to the data transfer register. It is often the case that such a procedure is executed back-to-back, and in such situations it is clear that even further performance benefits can be realised by using the approach of the preferred embodiment.
Another preferred embodiment where the use of the first scan chain controller instruction is particularly beneficial is where data is first scanned into the data transfer register, and then an instruction is loaded into the instruction transfer register, whereafter the instruction is executed to cause the data to be transferred to, for example, processor memory.
Accordingly, in such preferred embodiments, one of said circuit elements is a data transfer register, and the scan chain register is arranged to store the scan chain specifying value identifying the test scan chain coupled to the data transfer register, that test scan chain incorporating a shift register for shifting data into and out of said data transfer register. Preferably, data is first stored in the data transfer register using the second scan chain controller instruction, and then the first scan chain controller instruction is used to shift instruction data into the shift register, from where it is written into the instruction transfer register. Further, the microprocessor is preferably caused to execute the instruction specified by the instruction data, this causing the data in the data transfer register to be transferred to a location accessible by the microprocessor. This location may for example be another register or a memory position accessible by the microprocessor.
An example of how an application can be debugged using the instruction transfer register (ITR) and the data transfer register (DTR) accessed in accordance with the techniques of preferred embodiments is as follows. Firstly, it is assumed that the application is running, and that a watchpoint has been set up on a certain memory address. When the application code accesses that memory address, the watchpoint generates a hit and the processor stops executing instructions and waits for an instruction from the ITR. Using the techniques of the preferred embodiments, an instruction can be scanned into the ITR that, when executed by the processor, will cause the data value associated with that memory position to be stored in the DTR. This data value can then be checked by scanning it out from the DTR via the relevant test scan chain. If it is discovered that the data value has a wrong value, the right data value can be provided to the processor and the processor can then be restarted to check that the application completes execution correctly, thereby verifying that the source of the bug is related to the wrong data value.
The earlier mentioned IEEE Standard identified, amongst other things, two scan chain controller instructions called EXTEST and INTEST. The EXTEST instruction allowed testing of off-chip circuitry and board level interconnections, whilst the INTEST instruction allowed testing of the on-chip system logic. In preferred embodiments of the present invention, the EXTEST and INTEST instructions are used in a different manner. More particularly, the EXTEST instruction is used to invoke a process whereby old data is copied from a register into a shift register of a corresponding test scan chain, the old data is then shifted out of the shift register whilst new data is shifted into the shift register, and finally the new data is then written into the register. The INTEST instruction is used to invoke a process whereby the data within a register is copied into the shift register of a corresponding test scan chain, and then that data is shifted out of the shift register via the serial interface.
Accordingly, in preferred embodiments, the second scan chain controller instruction is EXTEST. Furthermore, the third scan chain controller instruction is preferably either INTEST or EXTEST.
Viewed from a second aspect, the present invention provides a method of operating an integrated circuit comprising a plurality of circuit elements, and a plurality of serial test scan chains each coupled to a different one of said circuit elements, the method comprising the steps of: responsive to a specified scan chain specifying value, selecting a corresponding one of said plurality of test scan chains; employing a decoder to decode scan chain controller instructions received at a serial interface of the integrated circuit; the decoder being responsive to a first scan chain controller instruction to specify a predetermined scan chain specifying value and a second scan chain controller instruction for decoding by the decoder.
Viewed from a third aspect, the present invention provides a computer program product carrying a computer program for controlling an integrated circuit in accordance with the method of the second aspect of the present invention.